Optimization of explicit-pulsed flip-flops for high performance

Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital design.