Process challenges in CMOS FEOL for 32nm node

With the navigation of ITRS, 32 nm technology node will be introduced around 2009. Scaling of CMOS devices from 45 nm to 32 nm node has come across significant barriers. In order to overcome these pitch-scaling induced barriers, it is demanded to integrate the most advanced process technologies into the product manufacturing. This paper will review and discuss new technology applications, which would be potentially integrated into the front end of line (FEOL) of 32 nm node. Some examples are discussed in the following areas: double patterning, direct silicon bonding (DSB), hybrid orientation substrate technology, metal/high-K (MHK) gate stacks, stress technologies and ultra-shallow junction (USJ).