Characteristics of sub-100nm ferroelectric field effect transistor with high-k buffer layer

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100 nm ferroelectric field effect transistor (FeFET) with high-k material as the buffer layer. Different configurations of gate stack are simulated and analyzed. It is shown that the structure of double-layer buffer can improve the device performance efficiently. Some important issues for FeFET scaling down are also discussed in this paper.