Embedded erase failure in NOR flash EEPROM memory

This paper presents the evaluation methods and findings of the hot temperature embedded erase failure on an embedded NOR flash EEPROM device. Automated Test Equipment (ATE) and bench evaluation revealed that the embedded erase failure was caused by compaction failure with high compaction pulse counts. Failure localization using memory bitmapping showed that the fail bitcells were populated at the edge of the flash array. Based on detailed electrical characterization and physical analysis, compaction failure was determined to be due to poor hot carrier injection (HCI) efficiency as a result of possible shallow trench isolation (STI) over-polish.