Plasma-process induced damage on 65nm logic VLSI manufacturing

Plasma-process induced damage (P2ID) is a serious yield and reliability concern with the continuous VLSI technical node shrinkage. In this paper, P2ID on 65 nm node VLSI manufacturing development is investigated. Plasma in high-density plasma deposition (HDP), preclean of physical vapor deposition (PVD) and reactive ion etching (RIE) processes have significant negative impact on P2ID. Respective improving actions have been implemented then on following processes: pre-metal dielectric (PMD) deposition, pre-clean before Cu barrier deposition and passivation etching for Al pad. As a result, P2ID free process has been achieved for logic 65 nm processes.