FPGA Implementation of High Speed FFT Algorithm Based on Split-Radix

Fast Fourier transform (FFT) is the collection of algorithms that performed the discrete Fourier transform (DFT). As a medium to perform the transform from time domain to frequency domain, FFT is widely used as an indispensible tool in signal processing applications. Split-radix algorithm is an appropriate algorithm for the implementation of FFT among all the effective algorithms of FFT. At the requirement of high speed, an algorithm that is best for high speed implementation is to be found. After researching all the relative algorithms, split-radix algorithm is chosen as the basic algorithm. In this paper, parallel processing and pipeline techniques are employed and proved to be a well-performed method. The proposed method performs well in the implementation of FPGA and satisfies the requirement of high speed. Results show the system latency of 13 clock periods and high efficiency in conserving hardware resources. The method put forward in this paper is extensible and can be applied to various applications.