Circuit driven delay optimization of EMODL carry lookahead adders

Delay minimization of carry look-ahead adders using the enhanced multiple output domino logic (EMODL), is investigated. Delay versus tree height, using an analytical transistor sizing technique, is analyzed, and the trade-off between the tree height and the number of stages is discussed. Four architectures for a 32-bit adder are compared at the layout level and experiments show that the number of stages is more critical for delay optimization. Mask level simulations predict an aggressive 2.1 ns critical path for the best architecture using a 1.2 micron CMOS technology. The simulation procedure is verified by fabrication.<>