Protocol Aware Test Methodologies Using Today's ATE

Deep Submicron shrinking IC geometries have enabled massive integration on an unprecedented level. Semiconductor companies with substantial IP libraries are able to manufacture a device that is a true "system on a chip" with diverse IP blocks in a single process on a single die. This massive level of integration has created new challenges for test engineers who are looking to efficiently and cost effectively bring up new SOC devices using automated test equipment. Todaypsilas conventional ATE has had tremendous integration leading to incredible speeds, pin count densities, all at lower costs, yet not even the most sophisticated state of the art tester can natively and in real time handshake with even the simplest chip I/O protocols such as JTAG, PCI, SPI, I2C or I2S, not to mention significantly more challenging I/O such as DDR, or PCIE. To solve these challenges the concept of protocol aware (PA) ATE has been introduced and is in the definition and design stages.