DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits

An IDDQ test sets all CMOS devices into a static digital state and then measures the tiny current leaking from power to ground. For this test to be useful, it is important to be able to conclusively verify IDDQ levels for individual design blocks via a simulation tool. This new methodology can help to conclusively verify that no floating nodes exist in a circuit which could hamper the usefulness of the system's IDDQ reliability test.