A 0.35μm CMOS sub-1V low-quiescent-current low-dropout regulator

A sub-1V CMOS low-dropout (LDO) voltage regulator with 103nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9V power supply, the output voltage is designed as 0.5V. The maximum output current of the LDO is 50mA at an output of 0.5V. The prototype of the LDO is fabricated with TSMC 0.35μm CMOS processes. The active area without pads is only 240μm × 400μm.