A method for delay fault self-testing of macrocells

Faults associated with delays may not cause functional failures at low performance tests. A method to stress macrocells under test, by adding certain delay cells around it, is proposed. Different configurations of delay cells are used to stress delay faults associated with respective paths through the macrocell. An example of the need for this is shown for a macrocell with asynchronous outputs such as an asynchronous-SRAM. This method would detect selected path delay faults, guaranteeing that the SRAM would function in the actual system and not just during test. The delay cells incorporated with the BIST netlist of the macrocell allow the self-testing of such faults during BIST operation.<>