A 6-bit 300-MS/s 2.7mW ADC based on linear voltage controlled delay line

This paper describes a novel ADC architecture based on time domain processing. By using a voltage controlled delay line, a linear transfer function of the input dependent delay is formed. The time delay difference is then compared to a reference to generate a digital code for the input. We have designed a 300-MS/s 6 bit ADC using this architecture in a 0.13 m standard digital CMOS. The simulation results show 36.6dB SNR, 34.1dB SNDR for 99MHz input, DNL≪0.2LSB, and INL≪0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply.