Low-latency scalable switch architecture for ATM/WDM high-speed networks

A new high capacity switching scheme for ATM/WDM networks is presented. The proposed architecture is contention-free, flexible and highly scalable. Switching performance is studied for data rates of up to 10 Gbit/sec/port, providing aggregated capacity of over 1 Terabit/sec. Simulation results show that low latency is achieved, yielding a powerful solution for high-performance packet-switch networks.