Real time reconfigurability for UWB receiver

Real time reconfigurability of the digital backend of UWB receiver has a potential to achieve significant power saving during the acquisition and synchronisation mode of receiver operation. This paper proposes a novel real time reconfigurability algorithm which can estimate number of parallel blocks required for the receiver operation for a particular channel condition and switches off the unwanted blocks. As a part of the real time reconfigurability algorithm, modified CLEAN and priority encoder algorithms are proposed for estimation and effective translation algorithms are developed in order to achieve significant reduction in receiver backend power consumption.