Achieving design closure in a typical mixed-signal ASIC; a Design-For-Test centric approach.

Achieving design closure in today's technologies (018μ and below) is generally a challenging task. Different objectives spanning timing, area, power, testability and numerous design rules needs to be addressed and fulfilled, all under tight project schedules as product lifetimes shrink. In this paper we look closer at the DFT (Design-For-Test) task from a top-level perspective; that is, we assume that the sub-blocks are already made testable themselves, and we look closer at the top-level integration process. Focus will be on design experience gained on a specific project and we will touch topics like clock-tree design, multiple power domains, different test modes, scan test and test response compression. Furthermore, we propose a DFT centric approach to top-level integration.