An advanced full path loop-back testing techniques for embedded RF Identification (RFID) System-on-a-Chip (SoC) applications

This paper presents the techniques of advanced full path loop-back test without the use of RF option in Automated Test Equipment (ATE) for embedded RF Identification (RFID) System-on-a-Chip (SoC) module. This investigation uses several methods to determine the characteristics of embedded RFID for SoC applications. Test vectors which are generated at control block (i.e. CPU) in the RFID SoC module are used in order to verify the full path test. In addition, an output of the transmitter part and an input of the receiver part in RFID transceiver are connected by using switches and attenuators for achieving the closed loop-back path. The captured signals at Rx output port of RF transceiver work properly because of applying full path loop-back test. The measured channel power flatness of 40 KHz input sinusoidal wave when channel is varied from 908.85 MHz to 913.65 MHz is shown to be less than 0.2 dBm in an RFID band, which is excellent stable for transmitting Tx signals. Moreover, 65 KHz sinusoidal output wave has −3 dB attenuated amplitude by the LPF having 64.5 KHz bandwidth at the both Tx and Rx. To achieve a linearity of Rx gain, Programmable Gain Amplifier (PGA) is controlled from 18 dB to 81 dB by using test vectors. These results show, for the first time, that an advanced full path loop-back testing technique has great performance to verify embedded RFID SoC and reduce the cost of test in ATE without the use of RF option.