A fast-response low-dropout regulator based on power-efficient low-voltage buffer

A power-efficient low-voltage buffer is presented. The proposed buffer contains a low-frequency zero generation circuit to perform frequency compensation and a slew-rate enhancement (SRE) circuit to provide large dynamic current for driving the pass device of the low-dropout (LDO) voltage regulator. What’s more, the proposed buffer, consuming small quiescent current over full load range, can work at low supply voltage, when comparing to conventional voltage buffer. A 1.2-V, 200-mA LDO with the proposed buffer has been designed in a 0.18-μm standard CMOS process. The low-voltage operation ability, high current efficiency and excellent transient response performance can be achieved. With a 1-μF ceramic output capacitor, the overshoot and undershoot of the output voltages are less than 20-mV when the load step changes between 1 and 200-mA in 100ns, while the current efficiency is up to 99.99% at full-load current.