Hardware reduction in digital MASH delta-sigma modulators via error masking

A reduced complexity (RC) digital Multi-stAge noise SHaping (MASH) delta-sigma modulator (DSM) was proposed in [1]. The sequence length is maximized by setting the LSB of the input to ldquo1rdquo; a long word is used for the first modulator in a MASH structure; shorter words are used in subsequent stages. Rules for selecting the wordlengths of each stage are presented in this paper. We show that an appropriate selection of the wordlength for each stage of the DSM can yield similar performance compared with a conventional MASH DSM, but with less hardware and lower power consumption.