In-situ jitter tolerance measurement technique for Serial I/O

A 10.2–12.5Gb/s CDR incorporating an on-die jitter modulation circuit that enables in-situ jitter tolerance testing is demonstrated in 65nm CMOS. Sinusoidal jitter is introduced into the CDR loop by modulating the control voltage of the LC-VCO and is programmable in amplitude and frequency. The modulation frequency range is 340kHz-104MHz with modulation amplitudes up to 44UIpp. The on-die jitter tolerance measurements correlate to conventional external jitter tolerance results within 10% across a 0.73–23.5MHz range.