A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS

An 8-bit 800MS/s time-interleaved pipeline ADC with SNDR of 47.8dB and 44.2dB for 1MHz and 400MHz inputs is presented. The techniques of Sub-ADC preamp sharing and reference voltage buffer current-reusing are proposed to minimize power consumption. The ADC implemented in 65nm digital CMOS process with an active area of 0.12mm² consumes 30mW from a 1.2V supply and achieves a FOM of 0.28pJ/conversion-step.