Design and analysis of a sequential ring counter for QCA implementation

The quantum-dot cellular automata (QCA) is currently being investigated as an alternative to CMOS VLSI. Its advantages such as smaller size, faster speed and lower consumption are very attractive. Unlike conventional computers in which information is transferred from one place to another by means of electrical current, QCA transfers information by propagating a polarization state. This paper proposes a detailed design analysis of a sequential ring counter circuit for quantum-dot cellular automata. The proposed design is based on the D-type flip-flop (D-FF) device. D-FF can be constructed by a QCA binary wire with four clocking zones. The aim is to maximize the circuit density and focus on a layout that is minimal in its use of cells.