Data memory management in partial dynamically reconfigurable systems

This paper aims at introducing a novel approach for the management of processor data memory in reconfigurable systems. The proposed approach allows the individual management of separated data and the dynamic update of the memory with a partial bitstream. By following this way it is possible to create a system in which several master components (e.g., soft-processors or hard-processors) can be dynamically configured and in which their memory can be dynamically changed. In the first section the reconfigurable scenario and its problems concerning to memory management will be introduced. The following sections will describe the state of the art and the development details of the tool that implements the proposed approach. Finally, a set of experimental results will be presented and conclusive remarks will be drawn.