Overview of DFT features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip

The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed defects. In addition, this paper addresses issues involved in SOC testing in the absence of IEEE 1500.