ESD-sensitive LNA design

A new ESD-sensitive LNA design method is presented, featuring S-parameter modelling and input matching network re-matching techniques for ESD+LNA full-chip design optimization. Design of 5 GHz LNA with 5 kV ESD protection in a 0.18 mum RFCMOS technology shows ESD-induced performance reduction in gain and noise figure up to -14.3% and +18% over a 1.8 GHz bandwidth range, which can be recovered by +76.3% and 63%, respectively, by using the proposed design technique.