A study on chip thinning process for ultra thin memory devices

Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus, the miniaturization of semiconductor devices is necessary, and chip thinning technologies are important key technologies to achieve it. The manufacturing steps for semiconductor devices are generally classified into steps for patterning semiconductor elements in a wafer, steps for thinning a wafer, steps for dicing semiconductor elements into chips and sealing the chips in packages. Wafers are thinned by means of mechanical in-feed grinding using a grindstone containing diamond particles, resulting in spiral grinding saw marks on the backside of the wafers. Dicing wafers always causes surface chipping, dicing saw marks on the chip side and backside chipping. Such defects on chip faces become sources of cracks, decreasing chip strength. Therefore, the manufacturing process of thin chips must achieve the requirement of no damage on all chip faces. We already proposed a novel wafer thinning process namely a dicing before grinding (DBG) and DBG + mirror finish process on 56^th ECTC [1], and also proposed a novel flip chip process for ultra thin chip on 57^th ECTC [2]. Incidentally, the thickness required for a semiconductor chip to work has not yet been determined. In this paper, the memory chip performance test results are described.