Bit-pattern optimization for accurate analysis of complex high-speed interfaces

The increased complexity of today's high speed systems is resulting in long pre-layout simulation times. Due to a multitude of design variables, many simulations are needed to locate the optimum design points. For a complex signal interface such as a DDR memory topology, one common way to measure and analyze channel jitter and noise is to plot the eye diagram of the desired output signal. The accuracy of the eye diagram is dependent on the input bit pattern used for the channel. Pre-layout analysis usually results in tens of thousands simulating. Performing these simulations with long bit streams is inefficient; at the same time performing pre- layout analysis with reduced set of bits will result in inaccurate analysis. In this paper, a novel algorithm based on evolutionary techniques such as genetic algorithms (GA) and swarm intelligence (SI) is described to find an optimized input bit pattern that can result in worst case channel jitter and noise. It has also been shown in the paper using few test cases that the optimized bit pattern is resilient to the channel topology changes i.e., the same optimized bit stream can be used for a large range of topologies with various combinations of design parameter settings.