Stability and Static Noise Margin Analysis of Low-Power SRAM

To overcome the read data destruction and to gain stability at Iow-V
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a seven-transistor (7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) SRAM cell. To illustrate the robust performance of an 8-bit SRAM statistical simulation and data analysis by considering the process variations and mismatch was conducted for every operation of the 8-bit SRAM. The measurement results show that the static noise margin (SNM) of the 7T SRAM cell is better than that of the 6T SRAM cell. The stability of the 8-bit 7T SRAM at low-V
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is also proved by testing the SRAM at 720 mV.