1.8 V to 5.0 V mixed-voltage-tolerant I/O buffer with 54.59% output duty cycle

This paper proposes a 1.8 V to 5.0 V mixed-voltage- tolerant I/O buffer. Unlike traditional mixed-voltage-tolerant I/O buffers, the proposed I/O buffer can transmit and receive the signal with high voltage level (VDDH) and low voltage level (VDDL) by employing an output stage composed of stacked PMOS and staked NMOS. Besides, an auxiliary charging circuit is employed to enhance the driving current Iqjj due to the slow mobility and body effect of the stacked PMOS. With the auxiliary driving mechanism, the duty cycle can be improved to be 54.59% at the worst simulation corner of [SS, 100degC]. The maximum output speed is 90/90/125/90 MHz given a load of 20 pF for VDDIO = 1.8/2.5/3.3/5.0 V. Moreover, the maximum static power consumption is simulated to be 749.73 nW.