A low-power CMOS multi-modulus dynamic frequency divider

A low-power CMOS multi-modulus dynamic frequency divider designed in TSMC 0.13-mum CMOS process is presented. The divider core comprises a synchronous 3-stage ring oscillator gated by the input clock signal. Basic divide-by-two mode is analyzed in detail to determine the working frequency range in terms of intrinsic divider delay elements. Divide-by-three and four frequency bands have also been observed and studied but at a lower input swing supplied by a programmable differential clock buffer. The frequency divider features a triple-modulus (/2/3/4) in the 5.4-6 GHz frequency band and dissipates 140 muW from a supply voltage of 1V. The frequency divider output phase noise is better that of the input clock source by 6, 9 and 11 dB for /2, /3 and /4 mode, respectively.