Reduced Z-datapath Cordic Rotator

In this article we propose a novel scheme based on virtually scaling-free COordinate Rotation DIgital Computer (CORDIC) algorithm to design a hardware efficient CORDIC rotator. For predicting rotation directions, less than 1/3
^rd
of the elementary rotational stages require classical CORDIC iteration. The rest of the iteration directions could be computed in parallel and the corresponding z-datapath could be eliminated. A 16-bit implementation of the processor requires 0.23 mm
²
silicon area and consumes 967.8 μW power when synthesized in 0.18 μm technology.