A simple technique to reduce clock jitter effects in continuous-time delta-sigma modulators

Continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In this paper, we present a simple technique to reduce clock jitter effects. The technique employs two delayed elements to generate a feedback current waveform with a fixed-width return-to-zero time period, followed a fixed-width time period for active feedback, which is followed by another variable return-to-zero time period subject to clock jitter. It has been shown in the paper through behavioral simulation models that this technique is very effective to reduce independent clock jitter effects.