Optimization techniques of AAC decoder on PACDSP VLIW processor

MPEG AAC has been widely used in variant applications and there are several standards developed based on the AAC. Considering to the trade-off between flexibility and performance, the DSP is adopted for implementation. The power consumption is an important issue for portable devices and there are limited resources on the DSP. However, due to the complex algorithms in AAC, design optimizations are required to reduce the power consumption and the memory utilization. Besides, the traditional algorithms usually not addressed on the optimization of VLIW based DSP. In this paper, we propose optimization techniques for the AAC decoding blocks on a VLIW based PACDSP processor. The realized decoder can be operated at a lower frequency of only 15 MHz and needs only 27 Kbytes of program memory and 27 Kbytes of data memory.