Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies

Increasing process variation can significantly degrade the write-ability of an SRAM. In this paper, we propose negative bit-line voltage technique to improve cell write-ability without using any on-chip or off-chip negative voltage source. Capacitive coupling is used to generate a transient negative voltage at the low bit-line during write operation. Simulations in 45nm PD/SOI technology show a 10³X reduction in the write-failure probability with the proposed technique.