Effect of context aware scheduler on TLB

Multiprocessing and multithreading increase frequencies of thread schedulings and context switches. Context switches can decrease the system throughput because they disturb locality of references and cause cache misses such as translation lookaside buffer (TLB), LI, and L2 misses. To reduce the overhead due to context switches, we focus on the advantage of threads which share the same memory address space (sibling threads). In switching sibling threads, the operating system (OS) does not have to switch their memory address spaces. Thus, we can omit a part of switching procedure and expect an efficient use of memory hierarchy. To utilize this advantage, we have proposed a context aware scheduler, which aggregates sibling threads. By using our scheduler, we can expect to reduce the switches of memory address spaces in executing multithreaded applications. Because switching memory address spaces results in TLB flushes on some kinds of processors, our scheduler can be effective in reducing TLB misses on such platforms. In this paper, we evaluate the effect of our context aware scheduler on reducing TLB misses. For this purpose, we run several multithreaded applications simultaneously with our context aware scheduler and measure the number of TLB misses. From these experiments, we conclude that our context aware scheduler is effective in reducing TLB misses and contributes to enhance the system throughput without imposing the degradation of throughput on any application.