Low-Leakage SMARTMOS 10W Technology At 0.13μm Node with Optimized Analog, Power and Logic Devices for SOC Design

SMARTMOS 10 W technology, which was developed based on 0.13-micron technology node, combines optimized power, analog and digital devices for wireless and consumer applications. As compared to the current state-of-the-art technologies, significant size shrink in power devices is achieved for cost reduction while the leakage is lowered by more than 20 times to minimize power consumption. Also, the technology doubles the performance of analog matching across FETs, resistors and capacitors. This technology is an excellent fit for all portable applications in which device size, battery life, sound quality and overall integration capability are key considerations.