Simulation of strain enhanced variability in nMOSFETs

We present a 3D simulation methodology aiming to capture the impact of strain on the line edge roughness (LER) induced variability in nMOSFETs. It includes both process and device simulation calibrated in respect of real 35 nm gate length nMOSFETs. Statistical LER of the gate pattern is introduced at the process simulation stage, and the impact of strain on the LER induced variability is investigated in Silicon nMOSFETs for the first time. Gate LER introduces both doping profile variability, and variability in the strain distribution in the channel, both contributing to the statistical variability in device electrical characteristics.