A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

A 3.2Gb/s single-ended current-integrating DFE receiver with 8b parallel data for 2-drop DRAM interface is implemented in a 0.18mum CMOS process. The reference voltage for the receiver is generated internally to reduce the external coupling noise. A single-loop implementation of sign-sign LMS algorithm is used to decide the single-tap equalization coefficient of the DFE receiver instead of the previous dual-loop implementation.