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An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation | IEEE Conference Publication | IEEE Xplore

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation


Abstract:

Locating the scan chain faults is very important for dedicated IC manufacturers to guide the failure analysis process for yield improvement. In this paper, we propose a n...Show More

Abstract:

Locating the scan chain faults is very important for dedicated IC manufacturers to guide the failure analysis process for yield improvement. In this paper, we propose a new symbolic simulation based scan chain diagnosis method to solve the scan chain diagnosis resolution problem as well as the multiple faults problem. The proposed method uses a new symbolic simulation with the faulty probabilities of a set of candidate faulty scan cells in a bounded range and to analyze the effects caused by faulty scan cells in good scan chains. In addition, we use the faulty information in good scan chains that are not contaminated by the faults while unloading scan out responses. In addition, a new score matching method is proposed to effectively handle multiple faults and to improve the diagnostic resolution by ranking the candidate scan cells in the candidate list. Experimental results demonstrate the effectiveness of the proposed method.
Date of Conference: 27 April 2008 - 01 May 2008
Date Added to IEEE Xplore: 07 May 2008
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Conference Location: San Diego, CA, USA

1. Introduction

Scan chain fault diagnosis is the process of identifying the defective scan cell in a scan chain. Several methods have been proposed to diagnose scan chain failures. Previous scan chain fault diagnosis methodologies are classified into two categories. The first category is hardware-based methods [1]–[4], which needs hardware modification beyond the basic scan design through special scan cell design or additional circuitry. These special designs are then used to facilitate the scan chain diagnosis process. However, these techniques may not be acceptable because of their area overhead, performance penalty and occurrence possibilities of other faults caused by additional circuits.

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