An Efficient Design Procedure for High-Speed Low-Power Dual-Modulus CMOS Prescalers

Dual-Modulus prescalers are high-speed blocks required for fractional PLL-based frequency synthesis. Besides the VCO, the prescaler is the other component that works at maximum frequencies and could often be the bottleneck in highspeed synthesizer design. This paper is an analysis of pulse- swallow prescalers and a design procedure that optimizes the speed and power for CMOS implementations. An 8/9 dual- modulus prescaler prototype IC was designed and fabricated in a 0.25μm process. Measured operating speed of 2.09GHz is obtained while minimizing the total power consumption to 4.5mW at 2.5V supply.