Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS

This paper presents measurement results on datapath delay distributions for data/instruction against Process, Voltage and Temperature (PVT) variations in 90 nm CMOS. Datapath delay has been measured using a completion signal generated at the end of datapaths with dual-rail logic according to data and instructions comprehensively for multiple Vdd and Temperature among several chips to show PVT variations. Measurement results were compared with the equivalent design in 0.35 um and demonstrated that the average delay variation against PVT variation was 16% for 90 nm where that was 10% for 0.35 mum CMOS.