A front-end processor for modems

A front-end processor constructed of an oversampling delta-sigma ADC/DAC (analog-to-digital converter/digital-to-analog converter) and a digital signal processor is described. The chip can handle a maximum of eight different processing modes for modem applications including the echo canceling scheme. The chip incorporates a voltage reference circuit, digital PLL (phase-locked loop), and a unique second interpolation circuit to realize both conventional QAM (quadrature amplitude modulation) demodulation and echo cancel-type demodulation. The chip is fabricated in a 1.5- mu m double-poly double-metal CMOS process. The chip size is 9.2 mm*7.2 mm, and the typical power consumption is 150 mW with a single +5.0-V power supply.<>