APC Methodology for Cpk improvement of HDP Deposition

As wafer size and number of process steps increase and feature sizes decrease, APC is increasingly being thought of as an integral component of any semiconductor manufacturing process, not just to reduce manual intervention but also to reduce excursions, increase the process yield and tool availability. This paper talks about the model, methodology, implementation and benefits realized from applying APC to the HDP (High Density Plasma) process. There are two layers in HDP process for oxide deposition, namely dielectric to isolate transistors and well, and the layer that electrically isolates the transistors from metal layers. Keeping the oxide thickness deposited on target and reducing wafer-wafer variation is critical not just for die yield but also for excursion prevention in downstream planar and etch processes. The APC algorithm for HDP recommends deposition time for each chamber that the wafers in an incoming lot will be processed in. The model uses advanced partitioning techniques to track not only the baseline deposition rates for each chamber for each tool, but also to compute the bias in the rate from one product to another. The deposition rate prediction for the incoming lot is based on two EWMA- standard deviation coupled filters, one for the chamber deposition rate and the other for the product bias. Thus, the recommended time for the wafers in a lot not only depends on which chamber the wafer will be processed in, but also on what the product is and what layer is being processed. The proposed presentation will describe the modeling approach and expand on the benefits realized from the application. This includes a reduction in wafer-to-wafer mean thickness range and 22% overall increase in Cpk. Benefits realized from other key quality characteristics such as increase in tool availability, and decrease in man-hours required for retargeting tools are also demonstrated.