An Addressable Test Structure for Geometrical Design Rules Characterization

A simple yet effective addressable test structure has been designed for the purpose of characterizing geometrical design rules. Design rule experiments are embedded in an array of isolation/continuity testers whose accesses are controlled by select transistors via periphery decoder circuits. The proposed decoding circuitry is very suitable for automatic layout generation. The test structure was fabricated using Spansion's 65 nm MirrorBittrade technology. Experimental results have demonstrated the effectiveness and usefulness of this test structure.