New energy recovery CMOS XNOR/XOR gates

In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.