Testing of LUT delay aliasing faults in SRAM based FPGAs using half-frequencies

In this paper, we present a technique for testing the delay aliasing faults associated with LUTs in SRAM based FPGAs. We compare the outputs of two identical LUTs when one is operated at half the frequency of the other. A Built in Self Test (BIST) circuitry consisting of a Test Pattern Generator, a Comparator, and the Circuit Under Test (CUT) is mapped on the FPGA. Application of input sequence vectors at half frequencies to the LUTs enable the detection of delay and aliasing faults which may go undetected by other techniques. The technique is verified using VHDL based simulations. The results are also experimentally verified using a Virtex II FPGA board.