Hybrid MCM Implementation for FIR Filters in FPGA Devices

Multiple Constant Multiplication (MCM) has been helpful in improving ASIC filter designs for years, but for FPGAs MCM does not always make the best use of resources. In particular, specialized embedded hardware modules intended to improve DSP circuits are not used. This paper will demonstrate that reserving a select set of coefficients from the MCM optimizations and implementing them with the available embedded hardware can reduce FPGA area utilization.