A Sub-Hundred NSEC DRAM Using the Taper Isolated Dynamic RAM Cell

The Taper Isolated dynamic RAM (TIRAM) cell is a ROM-like memory cell in which a single buried channel nMOS transistor provides two dynamically programmable threshold voltages by spatially confining a hole packet at the Si/SiO2 interface. The cell is very attractive for VLSI dRAMs because of its 3X density advantage over the 1-T cell, lOx lower leakage at high temperature compared to the 1-T cell and its immunity to soft errors [1]. A cross section of this cell accross the channel width is shown in Fig.la, with a potential distribution showing the hole storage well. Fig.lb shows how this cell is connected in a memory array.