Design for Improvement of Drop Impact Performance of Package-on Package

Package on Package is a packaging technology that one package is placed on top of another package to integrate different functionalities while still maintain same foot print size. Top package is normally for memory application while bottom package is for ASIC/RF application. PoP offers procurement flexibility, lower cost, avoiding KGD issues compared with system in package (SiP), stacked die etc. technologies. With the increasing demand of package-on-packages for telecommunication applications, some reliability issues have been raised. Such as warpage and solder joint reliability during thermal cycle and drop impact. In this paper, solder joint performance of PoP under drop impact was studied through FE modeling and experiment. It was found that the most critical solder joint is located at outmost corner of bottom packages. Failure occurs mostly at IMC of solder/PCB interface, followed by two interfaces of solder/substrate of top solder joints. Design guideline for improvement of drop impact performance was given. The knocking between bottom and top packages was also investigated. It showed that there is no knocking between bottom and top package if the gap between them is more than 10μm. The stress in solder joint was studied and it shows there is no significant difference even when there is knocking between two packages compared with large gap without knocking. The gap between two packages will affect solder joint formulation.