High Throughput VLSI Architecture for One Dimensional Median Filter

An attempt has been made to design a high throughput VLSI architecture for one dimensional median filter to suppress the impulse noise in real time signal and image processing applications. The proposed architecture is based on parallel and pipelined techniques. It takes 8-bit data serially and computes the median value in parallel and pipelined fashion out of a window having size of nine samples. This architecture is described in VerilogHDL and synthesized using commercially available 0.18mum CMOS technology at 1.8V power supply. The synthesis result gives an approximate core area and power of 1.2 mm² and 92.5 mW respectively at 100MHz clock frequency leading to a latency of thirteen clock cycles only.