IDDQ failures caused by stress-induced defects

IDDQ testing is an integrated circuit (IC) test technique that is based on measuring quiescent state power-supply current. It is the single most sensitive yet cost-effective test method and is currently adopted by most semiconductor manufacturers as part of their standard IC reliability test procedure. This paper presents the work that was carried out in studying and identifying possible process-induced root cause(s) resulting in IDDQ test failures of one particular semiconductor lot, thereafter will be referred to as outlier lot. This lot passes IC functional testing but exhibited higher IDDQ. Leakage current behavior and mechanisms are investigated and correlated with stress-induced defects found through physical failure analysis.